Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10

MUHAMMAD ULIN NUHA, HARI ARIEF DHARMAWAN, SETYAWAN PURNOMO SAKTI

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ABSTRAK

Desain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan. Paper ini memaparkan desain ADC SAR (Successive Approximation Register) 10-bit dua kanal simultan menggunakan Board FPGA (Field Programmable Gate Array) Altera DE10. FPGA dikonfigurasi untuk difungsikan sebagai sirkuit logika SAR dua kanal menggunakan bahasa VHDL (VHSIC-Very High Speed Integrated Circuit Hardware Description Language). Hasil pengujian menunjukkan kanal ADC_1 dan ADC_2 memiliki tingkat kesalahan rata-rata sebesar 1.05 % dan 0.90 %, tingkat akurasi sebesar 98.95 % dan 99.09 %, tingkat linearitas dengan koefisien korelasi sebesar 0.9999 dan 0.9999. Durasi waktu yang dibutuhkan dalam satu kali proses konversi ADC yaitu 104 μs. Didapatkan sampling-rate sebesar 9.6 KS/s. Daya yang dikonsumsi sebesar 842 mW. Kedua kanal ADC SAR yang telah dibuat mampu bekerja secara simultan.

Kata kunci: ADC, dua-kanal simultan, FPGA, SAR, VHDL

 

ABSTRACT

Desing of simultaneous multi-channel ADC (Analog to Digital Converter) architecture on the controller device can reduce the number of program instructions (tasks) that must be executed by microprocessor and can be used to form simultaneous measurements. This paper describes design of simultaneous two channel 10-bit SAR (Successive Approximation Register) ADC by using Board FPGA (Field Programmable Gate Array) Altera DE10. FPGA is configured using VHDL (VHSIC-Very High Speed Integrated Circuit Hardware Description Language) language to function as two channels SAR logic circuit. Test results show that ADC_1 and ADC_2 channels have average error of 1.05% and 0.90%, accuracy of 98.95% and 99.09%, linearity level with correlation coefficient of 0.9999 and 0.9999. Time duration in one ADC conversion process is 104 μs. The sampling rate obtained is 9.6 KS/s. Power consumed is 842 mW. Design of two channels SAR ADC that has been made can work simultaneously.

Keywords: ADC, two-channels simultaneous, FPGA, SAR, VHDL


Kata Kunci


ADC; dua-kanal simultan; FPGA; SAR; VHDL

Teks Lengkap:

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Referensi


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DOI: https://doi.org/10.26760/elkomika.v10i1.16

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ISSN (print) : 2338-8323 | ISSN (electronic) : 2459-9638

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